The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2007
Filed:
Aug. 16, 2004
Sally Y. L. Foong, Milpitas, CA (US);
Lim See-kee, Penang, MY;
Wong Kwet Nam, Penang, MY;
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
Cassettes for holding thin semiconductor wafers for safe handling are provided, along with an improved methodology for reducing the thickness of semiconductor wafers. Embodiments include a cassette for holding thin semiconductor wafers, having a plurality of sets of center and edge supports, the sets being spaced from each other a distance greater than a sag amount of the wafers. The thin wafers are supported in a predetermined reference plane, so that tools such as robots or automatic handlers can be programmed to pick them up without damaging them. In another embodiment, a double into single pitch wafer cassette is provided having a wafer entrance section with spacing twice as large between sets of edge supports as a conventional cassette, to accommodate the sag/warp of the thin wafers, and a 'flattening section' which guides and flattens the wafers between opposing edge supports as they are pushed into the cassette, such that the wafers are held substantially planar. Because the wafers are held substantially planar, they can be safely removed from the cassette by automatic tools. A methodology is also provided for reducing the thickness of a semiconductor wafer, comprising grinding the back side of the wafer to reduce its initial thickness to an intermediate thickness, and plasma etching the back side of the wafer to reduce the intermediate thickness to a final thickness. The two-step grinding/etching process is faster and less expensive than conventional multi-step grinding/polishing processes, because it requires less steps, each step is accomplished relatively quickly, and it employs standard grinding and etching equipment, rather than expensive dedicated equipment.