The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2006

Filed:

Jul. 23, 2004
Applicants:

Patrick J. Eichenseer, Austin, TX (US);

Hsi-chuan Chen, Fremont, CA (US);

Dennis Huang, Palo Alto, CA (US);

Inventors:

Patrick J. Eichenseer, Austin, TX (US);

Hsi-Chuan Chen, Fremont, CA (US);

Dennis Huang, Palo Alto, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

In accordance with a method for generating a trial placement plan for an IC having two or more identical modules, a floor plan reserves a separate area of identical size and shape for each of the identical modules, one of which is designated a 'master module' and the others designated 'clone modules'. A placement and routing (P&R) tool initially places all of the cell instances of the clone modules at the center of their reserved areas. The P&R tool then employs a conventional placement algorithm to iteratively adjust positions of cell instances of all other modules, including the master module within their reserved areas in a manner that tries to minimize net lengths. The P&R tool copies the placement within the master module area into the clone module areas either after every N>0 iterations of the placement algorithm and/or after the placement algorithm has completed placement for the master module area.


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