The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2006

Filed:

Nov. 26, 2003
Applicants:

Toshinobu Nakao, Takatsuki, JP;

Shinji Ozaki, Suita, JP;

Tomohisa Sezaki, Kyoto, JP;

Inventors:

Toshinobu Nakao, Takatsuki, JP;

Shinji Ozaki, Suita, JP;

Tomohisa Sezaki, Kyoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A scan test circuit is provided with a scan chain having n pieces of scan storage elements (n: integer, n>1); a scan clock generation circuit which is able to control a frequency of a first clock to be used for shifting data into the first to (n−1)th scan storage elements, and a frequency of a second clock to be used for shifting data into the n-th scan storage element and performing actual operation, independently from each other; and a scan selection internal signal generation circuit for generating a scan selection internal signal that is synchronized with the second clock.


Find Patent Forward Citations

Nakao, Toshinobu. (2006). Scan test control method and scan test circuit (U.S. Patent No. 7155649). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7155649

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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