The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2006

Filed:

May. 16, 2005
Applicants:

Kiyotaka Tabuchi, Kanagawa, JP;

Hideshi Miyajima, Kanagawa, JP;

Hideaki Masuda, Kanagawa, JP;

Inventors:

Kiyotaka Tabuchi, Kanagawa, JP;

Hideshi Miyajima, Kanagawa, JP;

Hideaki Masuda, Kanagawa, JP;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device, wherein an increase of a capacity between wiring layers is suppressed, reliability of wiring and property of withstand voltage of a diffusion prevention insulation film can be improved and the wiring resistance can be maintained low, is provided by comprising an interlayer insulation film formed on a substrate, a wiring formed on a trench pattern formed on the interlayer insulation film, and a diffusion prevention insulation film formed on an upper surfaces of the interlayer insulation film including the wiring and preventing diffusion of metal from the wiring; wherein the diffusion prevention insulation film has a middle layer between a lowermost layer and an uppermost layer, wherein the lowermost layer is formed so as to contact the upper surfaces of the interlayer insulation layer including the wiring, the uppermost layer constitutes an uppermost portion of the diffusion prevention insulation film, and the middle layer has a lower relative dielectric constant than those of the lowermost layer and the uppermost layer.


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