The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2006
Filed:
Nov. 18, 2004
Jon S. Choy, Austin, TX (US);
Tahmina Akhter, Austin, TX (US);
Jon S. Choy, Austin, TX (US);
Tahmina Akhter, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An integrated circuit includes a memory (). The memory () includes an array () of non-volatile memory cells. Each memory cell () of the array () includes a plurality of terminals comprising: a control gate, a charge storage region, a source, a drain, a well terminal, and a deep well terminal. Following an erase operation of the array (), the erase voltages are discharged from each of the memory cells. A discharge rate control circuit () controls the discharging of terminals of the memory cell. The discharge rate control circuit () includes a reference current generator () for providing a reference current. A first current mirror () is coupled to the reference current generator () and provides a first predetermined discharge current for discharging the control gate, drain, and source. A second current mirror () is coupled to the reference current generator () and provides a second predetermined discharge current for discharging the well terminals after the erase operation.