The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2006
Filed:
Mar. 17, 2005
Tae-hyun Kim, Gyeonggi-do, KR;
Byoung-moon Yoon, Gyeonggi-do, KR;
Won-jun Lee, Seoul, KR;
Yong-sun Ko, Gyeonggi-do, KR;
Kyung-hyun Kim, Seoul, KR;
Tae-hyun Kim, Gyeonggi-do, KR;
Byoung-moon Yoon, Gyeonggi-do, KR;
Won-jun Lee, Seoul, KR;
Yong-sun Ko, Gyeonggi-do, KR;
Kyung-hyun Kim, Seoul, KR;
Abstract
Methods of manufacturing a semiconductor device are provided. A trench is formed in a semiconductor substrate. A first field oxide layer is formed that partially fills the trench. The first field oxide layer defines an active region of the substrate that is adjacent to the trench. An upper portion of sidewalls of the trench extends upward beyond a surface of the first field oxide layer. A first liner is formed on the first field oxide layer and on the portion of the sidewalls of the trench that extend upward beyond the first field oxide layer. A second field oxide layer is formed on the first liner and fills the trench. The second field oxide layer and the first liner are each partially removed to expose a top adjacent surface and upper sidewalls of the trench along the active region of the substrate. A dielectric layer is formed on the exposed top adjacent surface and upper sidewalls of the trench. A gate electrode is formed on the dielectric layer.