The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2006

Filed:

Aug. 01, 2005
Applicants:

Hasan M. Nayfeh, Fishkill, NY (US);

Mahender Kumar, Fishkill, NY (US);

Sunfei Fang, LaGrangeville, NY (US);

Jakub T Kedzierski, Nashua, NH (US);

Cyril Cabral, Jr., Mahopac, NY (US);

Inventors:

Hasan M. Nayfeh, Fishkill, NY (US);

Mahender Kumar, Fishkill, NY (US);

Sunfei Fang, LaGrangeville, NY (US);

Jakub T Kedzierski, Nashua, NH (US);

Cyril Cabral, Jr., Mahopac, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 21/4763 (2006.01); H01L 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.


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