The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2006
Filed:
Aug. 29, 2003
Srinivasan Dasasathyan, Sunnyvale, CA (US);
Qiang Wang, Campbell, CA (US);
Srinivasan Dasasathyan, Sunnyvale, CA (US);
Qiang Wang, Campbell, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method () of placing inputs, outputs, and clocks in a circuit design can include assigning () initial locations to inputs and outputs of the circuit design, selecting () at least one component type for the circuit design, and generating () a cost function having parameters corresponding to the selected component type. The method further can include annealing () the selected component type using the cost function and determining design constraints () for the selected component type according to the annealing step. The method can repeat to process additional component types such that design constraints determined for each additional component type do not violate design constraints determined for prior component types.