The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7148728 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 12, 2006

Filed:

Oct. 01, 2004
Applicants:

Luc Montperrus, Montigny le Bretonneux, FR;

Philippe Boucard, le Chesnay, FR;

Jean-jacques Lecler, Cagnes sur Mer, FR;

Inventors:

Luc Montperrus, Montigny le Bretonneux, FR;

Philippe Boucard, le Chesnay, FR;

Jean-Jacques Lecler, Cagnes sur Mer, FR;

Assignee:

Arteris, Guyancourt Cedex, FR;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

Digitally controlled delay device, including a plurality of fine delay elements and a plurality of coarse delay elements, capable of delaying a signal generated by the device, by a fine or coarse delay respectively, the fine delay elements having delay times of between 60 and 170% of the mean of the fine delays and the sum of the fine delay times being greater than or equal to at least one coarse delay.


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Montperrus, Luc. (2006). Digital delay device, digital oscillator clock signal generator and memory interface (U.S. Patent No. 7148728). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7148728

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