The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2006
Filed:
Oct. 10, 2003
Richard G Cliff, Milpitas, CA (US);
Francis B Heile, Santa Clara, CA (US);
Joseph Huang, San Jose, CA (US);
David W Mendel, Sunnyvale, CA (US);
Bruce B Pedersen, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Kerry Veenstra, San Jose, CA (US);
Bonnie I Wang, Cupertino, CA (US);
Richard G Cliff, Milpitas, CA (US);
Francis B Heile, Santa Clara, CA (US);
Joseph Huang, San Jose, CA (US);
David W Mendel, Sunnyvale, CA (US);
Bruce B Pedersen, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Kerry Veenstra, San Jose, CA (US);
Bonnie I Wang, Cupertino, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface ('PCI') signaling protocol. Some of the registers on the device are closely coupled for data input and output to data signal input/output pins of the device. The clock signal input terminals of at least these registers are also closely coupled to the clock signal input pin of the device. Programmable input delay is provided between the data signal input/output pins and the data input terminals of the above-mentioned registers to help compensate for clock signal skew on the device.