The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7148556 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 12, 2006

Filed:

Nov. 09, 2004
Applicants:

Jonathan A. Shaw, Fort Collins, CO (US);

Sean Erickson, Fort Collins, CO (US);

Kevin Nunn, Fort Collins, CO (US);

Inventors:

Jonathan A. Shaw, Fort Collins, CO (US);

Sean Erickson, Fort Collins, CO (US);

Kevin Nunn, Fort Collins, CO (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01); H01L 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A p-type polysilicon resistor formed in the inter-level dielectric layer contains an implanted diode. A positive voltage applied to the diode modulates the depletion region of the diode and changes the absolute resistance of the p-type polysilicon resistor. This modulation occurs not only horizontally, but also vertically. The fact that the tunable resistor is a p-type polysilicon resistor means that this structure can easily be integrated into the process since polysilicon is used as a gate material for basic CMOS processing.


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