The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 2006
Filed:
Aug. 29, 2003
Thomas R. Bednar, Essex Junction, VT (US);
Timothy W. Budell, Milton, VT (US);
Patrick H. Buffet, Essex Junction, VT (US);
Alain Caron, South Burlington, VT (US);
James V. Crain, Jr., Milton, VT (US);
Douglas W. Kemerer, Essex Junction, VT (US);
Donald S. Kent, Colchester, VT (US);
Esmaeil Rahmati, South Burlington, VT (US);
Thomas R. Bednar, Essex Junction, VT (US);
Timothy W. Budell, Milton, VT (US);
Patrick H. Buffet, Essex Junction, VT (US);
Alain Caron, South Burlington, VT (US);
James V. Crain, Jr., Milton, VT (US);
Douglas W. Kemerer, Essex Junction, VT (US);
Donald S. Kent, Colchester, VT (US);
Esmaeil Rahmati, South Burlington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An integrated circuit chip having a contact layer that includes a plurality of Vdd, Vddx, ground and I/O contacts arranged in a generally radial pattern having diagonal and major axis symmetry and generally defining four quadrants. A multilayer X-Y power grid is located beneath the contact layer. A wiring layer is interposed between the contact layer and power grid to provide a well-behaved electrical transition between the generally radial Vdd, Vddx and ground contacts and the rectangular X-Y power grid. The interposed wiring layer includes concentric square rings of Vdd, Vddx and ground wires located alternatingly with one another. The Vddx wires are discontinuous between adjacent quadrants so that the magnitude of Vddx may be different in each quadrant of the chip if desired.