The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 2006
Filed:
Feb. 25, 2005
Tzung-han Lee, Taipei, TW;
Wen-jeng Lin, Pan-Chiao, TW;
Kuang-pi Lee, Fongyuan, TW;
Blue Larn, Taipei, TW;
Tzung-Han Lee, Taipei, TW;
Wen-Jeng Lin, Pan-Chiao, TW;
Kuang-Pi Lee, Fongyuan, TW;
Blue Larn, Taipei, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap layer. The conductive spacer is disposed on the sidewalls of the stacked gate structure. The oxide/nitride/oxide layer is disposed between the conductive spacer and the stacked gate structure and between the conductive spacer and the substrate. The buried doping regions are disposed in the substrate outside the conductive spacer on each side of the stacked gate structure. The control gate is disposed over the stacked gate structure and electrically connected to the conductive spacer. The insulating layer is disposed between the buried doping layer and the control gate.