The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2006

Filed:

Nov. 06, 2003
Applicants:

Muralidhar R. Kudlugi, Framingham, MA (US);

Charles W. Selvidge, Wellesley, MA (US);

Inventors:

Muralidhar R. Kudlugi, Framingham, MA (US);

Charles W. Selvidge, Wellesley, MA (US);

Assignee:

Mentor Graphics Corporation, Wilsonville, OR (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

In an emulation system, a method is provided to schedule evaluations of state elements and memory elements receiving signals from multiple asynchronous clock domains, such that causality and hold time requirements are satisfied. In addition, a method is provided such that logic signals responsive to multiple asynchronous clock domains are transported along separate single domain path of substantially equal transit times. In one implementation, the scheduling method computes departure times and ready times for output and input terminals of logic modules, such as FPGAS.


Find Patent Forward Citations

Kudlugi, Muralidhar. (2006). Functional verification of logic and memory circuits with multiple asynchronous domains (U.S. Patent No. 7143377). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7143377

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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