The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7143371 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 28, 2006

Filed:

Apr. 27, 2004
Applicants:

Robert J. Allen, Jericho, VT (US);

Evanthia Papadopoulou, White Plains, NY (US);

Mervyn Yee-min Tan, South Burlington, VT (US);

Inventors:

Robert J. Allen, Jericho, VT (US);

Evanthia Papadopoulou, White Plains, NY (US);

Mervyn Yee-Min Tan, South Burlington, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.


Find Patent Forward Citations

Allen, Robert. (2006). Critical area computation of composite fault mechanisms using voronoi diagrams (U.S. Patent No. 7143371). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7143371

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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