The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2006

Filed:

Jun. 13, 2003
Applicants:

Ke-wei Su, Shan-Hua, TW;

Cheng Hsiao, Chiai, TW;

Jaw-kang Her, Hsinchu, TW;

Inventors:

Ke-Wei Su, Shan-Hua, TW;

Cheng Hsiao, Chiai, TW;

Jaw-Kang Her, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for reducing sidewall capacitance by 25% or more in an STI structure is described. A conformal barrier layer is deposited on sloped sidewalls in a shallow trench within a substrate. The trench is filled with a low k dielectric material which is planarized and etched back. Next a barrier cap layer is deposited that is different than the underlying low k dielectric layer. In one embodiment, the barrier cap layer is a SiCOH material that is modified for enhanced CMP performance that yields fewer surface scratches and defects. A nitride etch stop layer and a pad oxide are removed above an active area on the substrate to afford the final STI structure. Optionally, the barrier cap layer is omitted and the low k dielectric layer extends slightly above the substrate level. Total parasitic capacitance in the resulting MOS device is reduced by 15% or more.


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