Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program

Abstract

A disclosed semiconductor memory device includes multilevel memory cells in which data in the cells is arranged according to a coding method that allows error correction. One disclosed device has multilevel memory cells arranged so as to correspond to a physical address space, each cell storing 2levels of data, each expressed by n (n≧2) number of bits (X, X, Xn). When an input logical address is converted into a physical address, a determination is made whether the logical address space matches the physical address space. If there is not a match, the most significant bit Xis specified once using a reference value, and the specified bit is output from one of the cells corresponding to the physical address. If there is not match, the bits (X, . . . , Xn) are specified by an n—time specifying operation using maximum n number of different reference values.