The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2006

Filed:

Aug. 02, 2002
Applicants:

Kazuki Mizushima, Tokyo, JP;

Ichiro Shiono, Tokyo, JP;

Kenji Yamaguchi, Tokyo, JP;

Inventors:

Kazuki Mizushima, Tokyo, JP;

Ichiro Shiono, Tokyo, JP;

Kenji Yamaguchi, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 31/072 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor substrate, a field effect transistor and their manufacturing methods provided with, in order to lower penetrating dislocation density and reduce surface roughness to a practical level, an Si substrate, a first SiGe layeron the Si substrate, and a second SiGe layerarranged on the first SiGe layer either directly or with an Si layer in between; wherein, the first SiGe layer has a film thickness that is thinner than twice the critical film thickness, which is the film thickness at which dislocation occurs resulting in lattice relaxation due to increased film thickness, the Ge composition ratio of the second SiGe layer is at least lower than the intralayer maximum value of the Ge composition ratio in the first SiGe layer or in the first SiGe layer at the contact surface with the Si layer, and the second SiGe layer has an incremental composition region in which the Ge composition ratio gradually increases towards the surface at least in a portion thereof.


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