The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2006
Filed:
Jun. 01, 2004
John J. Wang, San Jose, CA (US);
Siu May Ho, Sunnyvale, CA (US);
Jeffrey P. Erhardt, San Jose, CA (US);
Srikanth Sundararajan, Sunnyvale, CA (US);
David C. Newbury, Saratoga, CA (US);
Shivananda S. Shetty, Sunnyvale, CA (US);
Paul J. Steffan, Elk Grove, CA (US);
Franklyn Shihyu Wu, Berkeley, CA (US);
John J. Wang, San Jose, CA (US);
Siu May Ho, Sunnyvale, CA (US);
Jeffrey P. Erhardt, San Jose, CA (US);
Srikanth Sundararajan, Sunnyvale, CA (US);
David C. Newbury, Saratoga, CA (US);
Shivananda S. Shetty, Sunnyvale, CA (US);
Paul J. Steffan, Elk Grove, CA (US);
Franklyn Shihyu Wu, Berkeley, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A system and method for wafer level global bitmap characterization include determining chip level defect data bitmaps from a semiconductor wafer, and consolidating the chip level defect data bitmaps into a global wafer level bitmap that characterizes substantially the entire wafer failure configuration. The global wafer level bitmap is then analyzed and compared with other global wafer level bitmaps to develop correlations thereamong and develop global wafer level bitmap definitions for conducting at least one of wafer-to-wafer, boat-to-boat, and lot-to-lot process analysis based upon the global wafer level bitmap definitions.