The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2006

Filed:

May. 05, 2005
Applicants:

Yasuo Murakuki, Kyoto, JP;

Hiroshige Hirano, Nara, JP;

Yasushi Gohou, Osaka, JP;

Masahiko Sakagami, Kyoto, JP;

Kunisato Yamaoka, Osaka, JP;

Shunichi Iwanari, Kyoto, JP;

Tetsuji Nakakuma, Shiga, JP;

Takashi Miki, Hyogo, JP;

Inventors:

Yasuo Murakuki, Kyoto, JP;

Hiroshige Hirano, Nara, JP;

Yasushi Gohou, Osaka, JP;

Masahiko Sakagami, Kyoto, JP;

Kunisato Yamaoka, Osaka, JP;

Shunichi Iwanari, Kyoto, JP;

Tetsuji Nakakuma, Shiga, JP;

Takashi Miki, Hyogo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage areaformed from electrically-rewritable nonvolatile memory and a second setting function storage areaformed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address registerand transfer of operation mode setting information to an operation mode registerare selectively performed.


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