The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2006
Filed:
Feb. 25, 2003
Jade M. Kizer, Mountain View, CA (US);
Benedict C. Lau, San Jose, CA (US);
Roxanne T. VU, San Jose, CA (US);
Huy M. Nguyen, San Jose, CA (US);
Leung Yu, Santa Clara, CA (US);
Adam Chuen-huei Chou, San Jose, CA (US);
Jade M. Kizer, Mountain View, CA (US);
Benedict C. Lau, San Jose, CA (US);
Roxanne T. Vu, San Jose, CA (US);
Huy M. Nguyen, San Jose, CA (US);
Leung Yu, Santa Clara, CA (US);
Adam Chuen-Huei Chou, San Jose, CA (US);
Rambus Inc., Los Altos, CA (US);
Abstract
A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines. The biasing circuit comprising a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.