The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 2006
Filed:
Aug. 02, 2005
Li-qun Xia, Santa Clara, CA (US);
Mei-yee Shek, Mountain View, CA (US);
Troy Kim, Mountain View, CA (US);
Vladamir Zubkov, Mountain View, CA (US);
Ritwik Bhatia, Sunnyvale, CA (US);
Li-Qun Xia, Santa Clara, CA (US);
Mei-Yee Shek, Mountain View, CA (US);
Troy Kim, Mountain View, CA (US);
Vladamir Zubkov, Mountain View, CA (US);
Ritwik Bhatia, Sunnyvale, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
A method of forming a sidewall spacer on a gate electrode is described. The method includes generating a first plasma from a silicon containing precursor and oxide precursor, and forming a silicon oxy-nitride layer on the sidewall of the gate electrode. The method also includes generating a second plasma from the silicon containing precursor and a nitrogen precursor, and forming a nitride layer on the silicon oxy-nitride layer. The silicon containing precursor can flow continuously between the generation of the first and the second plasmas. Also, a method of forming a sidewall spacer on the side of a gate electrode on a substrate. The method includes forming an oxy-nitride layer on the sidewall, and forming a nitride layer on the oxy-nitride layer, where the substrate wafer is not exposed to air between the formation of the layers.