Application of post-pattern resist trim for reducing pocket-shadowing in srams

Abstract

Methods () are disclosed for minimizing the effect of pocket shadowing in the fabrication of an angled pocket implant () extending underlying a gate region () of a transistor (), particularly in SRAM devices (). The pocket shadowing is minimized by initially forming a relatively thick resist layer () overlying the semiconductor device (), then the resist layer thickness () is reduced (trimmed) to a reduced thickness () by using a subsequent post-development dry or wet resist-reduction etch process (). The etch process () also increases corner rounding (), thereby reducing pocket shadowing of the angled implant from nearby features or the resist (). The pocket shadow reduction may be accomplished by first forming () the relatively thick resist layer () overlying the semiconductor device (). The resist layer () is then wet and/or dry etched () to trim the resist thickness () and to round the corners () of the resist (). In combination, these changes reduce shadowing of angled implants from nearby structures and resist edges. The method may further comprise a first implant () (e.g., an LDD implant) before the resist etch trim (), and a second angled pocket implant () after the etch trim () to permit individually optimizing the resist thickness and CD for each implant. Thus, only one lithography step is required, while cross diffusion of the LDD implant is mitigated. Transistors (and, orand) formed in this manner may yield improved performance when incorporated into SRAM () since the probability that such transistors will be more closely matched is increased.