The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2006
Filed:
Dec. 23, 2003
Per H. Hammarlund, Hillsboro, OR (US);
Stephan Jourdan, Portland, OR (US);
Sebastien Hily, Hillsboro, OR (US);
Aravindh Baktha, Portland, OR (US);
Hermann Gartler, Portland, OR (US);
Per H. Hammarlund, Hillsboro, OR (US);
Stephan Jourdan, Portland, OR (US);
Sebastien Hily, Hillsboro, OR (US);
Aravindh Baktha, Portland, OR (US);
Hermann Gartler, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffer before retirement; and setting a status bit associated with the entry in said store buffer, if the address is in the cache in either exclusive or modified state. The method further includes immediately writing the entry to the first-level cache at or after retirement when the status bit is set; and de-allocating the entry from said store buffer at retirement. The method further may comprise resetting the status bit if the cacheline is allocated over or is evicted from the cache before the store buffer entry attempts to write to the cache.