The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2006
Filed:
Dec. 17, 2003
Charles Jay Alpert, Round Rock, TX (US);
Rama Gopal Gandham, Poughkeepsie, NY (US);
Milos Hrkic, Princeton, NJ (US);
Stephen Thomas Quay, Austin, TX (US);
Charles Jay Alpert, Round Rock, TX (US);
Rama Gopal Gandham, Poughkeepsie, NY (US);
Milos Hrkic, Princeton, NJ (US);
Stephen Thomas Quay, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A mechanism for constructing Steiner trees using simultaneous blockage avoidance, delay optimization, and design density management are provided. An initial tiled timing-driven Steiner tree is obtained for an integrated circuit design. The Steiner tree is broken into 2-paths for which plates are generated designated the permissible area in which a Steiner point may migrate. Each 2-path is optimized by calculating a cost for each tile in the plate as a function of an environmental cost, a tile delay cost, and a trade-off value. A minimum cost tile is then selected as the point to which the Steiner point in the 2-path, if any, is to migrate. Once each 2-path is processed in this manner, routing is performed so as to minimize the cost at the source. This process may be iteratively repeated with new trade-off values until all of the nets have zero or positive slew.