The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2006
Filed:
Dec. 31, 2001
David L. Hill, Cornelius, OR (US);
Deborah T. Marr, Portland, OR (US);
Dion Rodgers, Hillsboro, OR (US);
Shiv Kaushik, Portland, OR (US);
James B. Crossland, Banks, OR (US);
David A. Koufaty, Portland, OR (US);
David L. Hill, Cornelius, OR (US);
Deborah T. Marr, Portland, OR (US);
Dion Rodgers, Hillsboro, OR (US);
Shiv Kaushik, Portland, OR (US);
James B. Crossland, Banks, OR (US);
David A. Koufaty, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Coherency techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes a cache, execution logic to execute an instruction having an operand indicating a monitor address and a bus controller. In one embodiment, the bus controller is to assert a preventative signal in response to receiving a memory access attempting to gain sufficient ownership of a cache line associated with said monitor address to allow modification of said cache line without generation of another transaction indicative of the modification. In another embodiment, the bus controller is to generate a bus cycle in response to the instruction to eliminate any ownership of the cache line by another processor that would allow a modification of the cache line without generation of another memory access indicative of the modification.