The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7127483 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 24, 2006

Filed:

Dec. 26, 2001
Applicants:

Andrew J. Beaumont-smith, Cambridge, MA (US);

Sridhar Samudrala, Westboro, MA (US);

Inventors:

Andrew J. Beaumont-Smith, Cambridge, MA (US);

Sridhar Samudrala, Westboro, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

The specification discloses a structure of and a method of operating a subtractive division (SD) cell where a portion of the partial remainder or estimated partial remainder directly indicates the next quotient digit. More particularly, by sufficiently constraining the prescaled range for each possible divisor, only a few bits of the partial remainder (the exact number dependent upon the radix), along with their related carries (if any), directly indicate the value of the next quotient digit. Because fewer bits of the partial remainder are needed to make this determination than needed in related art devices, and further because no look-up table or hard-coded decision tree is required, calculation time within each SD cell is shorter than related art devices. Having a shorter calculation time within each SD cell allows for either completion of a greater number of SD cells within each clock cycle, or completion of the calculation to full precision in less time.


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Beaumont-Smith, Andrew. (2006). Method and system of a microprocessor subtraction-division floating point divider (U.S. Patent No. 7127483). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7127483

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