The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2006

Filed:

Jul. 19, 2002
Applicants:

William P. Evans, Catonsville, MD (US);

C. Thomas Gray, Apex, NC (US);

Scott Huss, Cary, NC (US);

Inventors:

William P. Evans, Catonsville, MD (US);

C. Thomas Gray, Apex, NC (US);

Scott Huss, Cary, NC (US);

Assignee:

Rambus, Inc., Los Altos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a method and mechanism for regenerating the clock signal and recovering the data of a serial bit data stream. According to an embodiment, a circuit for recovering data from a serial bit stream may include a de-serializer configured for reclocking the serial bit stream using at least one reclocking signal, having a frequency with a phase, and de-serializing the serial bit stream into at least two bit streams. The circuit may further include a clock recovery loop filter having a second order filter coupled with the deserializer. The clock recovery loop filter may be configured for determining whether the de-serializer is reclocking the serial bit data stream at an optimum location and for generating at least one control signal to adjust the phase of the frequency of the at least one reclocking signal if the de-serializer is not reclocking the serial bit data stream at the optimum location. The circuit may also include a phase interpolator coupled with the clock recovery loop filter and the de-serializer, configured for generating the at least one reclocking signal in accordance with the at least one control signal.


Find Patent Forward Citations

Loading…