The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2006
Filed:
Jul. 29, 2004
Robert J. Allen, Jericho, VT (US);
Steven G. Lovejoy, South Burlington, VT (US);
Kevin W. Mccullen, Essex Junction, VT (US);
Robert J. Allen, Jericho, VT (US);
Steven G. Lovejoy, South Burlington, VT (US);
Kevin W. McCullen, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method () of placing a to-be-placed integrated circuit macro () adjacent one or more already-placed macros () aboard an integrated circuit chip (). The method includes the step of performing a canonical ordering of the edges of the to-be-placed and already placed macros. Then, an edge constraint vector () is generated for each active edge () of the already-placed macro(s) and each edge of the to-be-placed macro. Each of the edge constraint vectors of the to-be-placed macro is compared to each edge constraint vector of the active edge(s) using a string matching algorithm so as to determine whether any edges of the to-be-placed macro are compatible with any active edges of the already-placed macro(s). The method may be implemented in a CAD system ().
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile