The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2006

Filed:

Sep. 21, 2000
Applicants:

William C. Moyer, Dripping Springs, TX (US);

Jeffrey W. Scott, Austin, TX (US);

Brett W. Murdock, Austin, TX (US);

Inventors:

William C. Moyer, Dripping Springs, TX (US);

Jeffrey W. Scott, Austin, TX (US);

Brett W. Murdock, Austin, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Embodiments of the present inventions relate to processors having sequential address indicator signals, also referred to as sequence signals, for indicating when accessed addresses are sequential. One embodiment relates to a processing system for accessing memory having an address bus for providing a current address and a previous address to memory, a data bus, an execution unit, and a decode control unit. The processing system further includes a fetch unit, coupled to the execution unit, the decode control unit, the address bus, and the data bus, for generating a first sequence signal that when negated indicates that the current address may not be sequential to the previous address, a second sequence signal that when negated indicates that the current address is not sequential to the previous address, and a third sequence signal that when negated indicates that the current address, if it is an instruction address, is not sequential to the previous address that was an instruction address.


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