The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2006

Filed:

Apr. 25, 2002
Applicants:

Chen-jung Tsai, Hsin-Chu, TW;

Jui-chung Lee, Yun-Lin, TW;

Chih-wen Lin, Hsin-Chu, TW;

Inventors:

Chen-Jung Tsai, Hsin-Chu, TW;

Jui-Chung Lee, Yun-Lin, TW;

Chih-Wen Lin, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor packaging device comprises a carrier having at least a cavity or a slot thereon. At least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier, which comprises first via-conductor connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second via-conductor therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first via-conductor are electrically connected with the conductive layout lines, the second via-conductor, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads, and at least a second chip is affixed to the flip-chip pads through a plurality of second solder balls.


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