The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2006

Filed:

Apr. 02, 2004
Applicants:

Jeong-nam Han, Seoul, KR;

Woo-gwan Shim, Yongin-si, KR;

Woo-sung Han, Seoul, KR;

Chang-ki Hong, Seongnam-si, KR;

Sang Jun Choi, Seoul, KR;

Inventors:

Jeong-Nam Han, Seoul, KR;

Woo-Gwan Shim, Yongin-si, KR;

Woo-Sung Han, Seoul, KR;

Chang-Ki Hong, Seongnam-si, KR;

Sang Jun Choi, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 21/461 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device using a polysilicon layer as an etching mask includes: (a) forming an interlayer dielectric over a semiconductor substrate; (b) forming a polysilicon layer pattern over the interlayer dielectric; (c) forming a contact hole in the interlayer dielectric by etching the interlayer dielectric using the polysilicon layer pattern as an etching mask; (d) removing the polysilicon layer pattern by an etching process that has a large etching selectivity of the polisilicon layer with respect to the interlayer dielectric and about 3% or less etching uniformity; and (e) forming a contact by filling the contact hole with a conductive material.


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