The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7118955 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 10, 2006

Filed:

Dec. 10, 2004
Applicants:

Jurgen Amon, Dresden, DE;

Jurgen Faul, Radebeul, DE;

Thomas Ruder, Dresden, DE;

Thomas Schuster, Dresden, DE;

Inventors:

Jurgen Amon, Dresden, DE;

Jurgen Faul, Radebeul, DE;

Thomas Ruder, Dresden, DE;

Thomas Schuster, Dresden, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8244 (2006.01);
U.S. Cl.
CPC ...
Abstract

Method for the production of a semiconductor structure comprising a plurality of gate stacks on a semiconductor substrate which serve as control electrodes for a respective selection transistor of a corresponding memory cell comprising a storage capacitor. Gate stacks are provided next to one another on the substrate provided with a gate dielectric wherein the gate stacks have a lower first layer made of polysilicon, an overlying second layer made of metal silicide, and an upper layer made of silicon nitride. A sidewall oxide is formed on uncovered sidewalls of the first and second layers of the gate stacks, and at least partly the sidewall oxide is removed on those sidewalls of the gate stacks serving as a control electrode which are remote from the associated storage capacitor. Silicon nitride sidewall spacers are then formed on the gate stacks.


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Amon, Jurgen. (2006). Method for the production of a semiconductor substrate comprising a plurality of gate stacks on a semiconductor substrate, and corresponding semiconductor structure (U.S. Patent No. 7118955). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7118955

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