The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2006

Filed:

Sep. 30, 2004
Applicants:

Joze E. Antol, Hamburg, PA (US);

Philip William Seitzer, Bethlehem, PA (US);

Daniel Patrick Chesire, Winter Garden, FL (US);

Rafe Carl Mengel, Hamburg, PA (US);

Vance Dolvan Archer, Asbury Park, NJ (US);

Thomas B. Gans, Doylestown, PA (US);

Taeho Kook, Orlando, FL (US);

Sailesh M. Merchant, Macungie, PA (US);

Inventors:

Joze E. Antol, Hamburg, PA (US);

Philip William Seitzer, Bethlehem, PA (US);

Daniel Patrick Chesire, Winter Garden, FL (US);

Rafe Carl Mengel, Hamburg, PA (US);

Vance Dolvan Archer, Asbury Park, NJ (US);

Thomas B. Gans, Doylestown, PA (US);

Taeho Kook, Orlando, FL (US);

Sailesh M. Merchant, Macungie, PA (US);

Assignee:

Agere Systems, Inc., Allentown, PA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 23/053 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed herein are novel support structures for pad reinforcement in conjunction with new bond pad designs for semiconductor devices. The new bond pad designs avoid the problems associated with probe testing by providing a probe region that is separate from a wire bond region. Separating the probe regionfrom the wire bond regionand forming the bond padover active circuitry has several advantages. By separating the probe regionfrom the wire bond region, the wire bond regionis not damaged by probe testing, allowing for more reliable wire bonds. Also, forming the bond padover active circuitry, including metal interconnect layers, allows the integrated circuit to be smaller.


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