The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2006

Filed:

May. 17, 2004
Applicants:

Werner Juengling, Boise, ID (US);

Steven M. Mcdonald, Meridian, ID (US);

Kunal R. Parekh, Boise, ID (US);

Inventors:

Werner Juengling, Boise, ID (US);

Steven M. McDonald, Meridian, ID (US);

Kunal R. Parekh, Boise, ID (US);

Assignee:

Micron Technology, Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication and patterning of bond pads and redistribution layers is conducted simultaneously over a fuse box region to form and/or remove materials that are directly over the fuse box region.


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Juengling, Werner. (2006). Methods of forming semiconductor constructions (U.S. Patent No. 7115512). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7115512

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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