The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 26, 2006
Filed:
Aug. 30, 2001
Deep K. Buch, Folsom, CA (US);
Zhenjun HU, Folsom, CA (US);
Neil Schaper, Folsom, CA (US);
David Zhao, Rancho Cordova, CA (US);
Vladimir M. Pentkovski, Folsom, CA (US);
Deep K. Buch, Folsom, CA (US);
Zhenjun Hu, Folsom, CA (US);
Neil Schaper, Folsom, CA (US);
David Zhao, Rancho Cordova, CA (US);
Vladimir M. Pentkovski, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A multiprocessor-scalable streaming data server arrangement in a multiprocessor data server having N processors, N being an integer greater than or equal to 2, includes implementing N NICs (Network Interface Cards), a first one of the N NICs being dedicated to receiving an incoming data stream. An interrupt from the first one of the N NICs is bound to a first one of the N processors and an interrupt for an nth NIC is bound to an nth processor, 0<n<=N. A DPC (Deferred Procedure Call) for the nth NIC is bound to the nth processor. M client connections may be tightly coupled to the nth processor via the nth NIC, M being a positive integer. P server threads may be bound to specific ones of a second through N processors. L1 (Level 1) and L2 (Level 2) caches may be defined for each of the N processors, instructions and temporal data being stored in L2 caches of the N processors and non-temporal data being stored in L1 caches of the N processors, bypassing the L2 caches.