The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 26, 2006
Filed:
Oct. 29, 2004
Hee-soon Chae, Gyeonggi-do, KR;
Chung-woo Kim, Gyeonggi-do, KR;
Kwang-youl Seo, Seoul, KR;
Tae-hyun Han, Gyeonggi-do, KR;
Byung-chul Kim, Gyeongsangnam-do, KR;
Joo-yeon Kim, Ulsan-si, KR;
Hee-soon Chae, Gyeonggi-do, KR;
Chung-woo Kim, Gyeonggi-do, KR;
Kwang-youl Seo, Seoul, KR;
Tae-hyun Han, Gyeonggi-do, KR;
Byung-chul Kim, Gyeongsangnam-do, KR;
Joo-yeon Kim, Ulsan-si, KR;
Samsung Electronics Co., Ltd., Suwon-Si, KR;
Kwang-Youl Seo, Jungnang-Gu, KR;
Abstract
Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.