The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2006

Filed:

Nov. 07, 2005
Applicants:

Iosif R. Korsunsky, Harrisburg, PA (US);

Kevin E. Walker, Hershey, PA (US);

Lewis R. Johnson, Dover, PA (US);

Tod M. Harlan, Mechanicsburg, PA (US);

Robert W. Brown, Harrisburg, PA (US);

Richard Malehorn, Ii, York, PA (US);

Inventors:

Iosif R. Korsunsky, Harrisburg, PA (US);

Kevin E. Walker, Hershey, PA (US);

Lewis R. Johnson, Dover, PA (US);

Tod M. Harlan, Mechanicsburg, PA (US);

Robert W. Brown, Harrisburg, PA (US);

Richard Malehorn, II, York, PA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01R 13/502 (2006.01);
U.S. Cl.
CPC ...
Abstract

An electrical device () for interconnecting two parallel printed circuit boards at a large distance includes a plug connector (), a receptacle connector ('), and a mating extender () disposed between the plug connector and the receptacle connector. The mating extender includes a subassembly of wafer (), a pair of identical caps () disposed on the top and bottom portions of the subassembly of wafer, and a pair of shroud-halves () sliding on the subassembly of the wafer. The subassembly of wafer is made up of a number of wafer modules () parallel with each other. Each wafer module has a wafer support () and a number of contacts () embedded in the wafer support.


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