The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 2006
Filed:
Jul. 27, 2004
Takashi Kobayashi, Tokorozawa, JP;
Yasushi Goto, Kokubunji, JP;
Tokuo Kure, Hinodemachi, JP;
Hideaki Kurata, Kokubunji, JP;
Hitoshi Kume, Musashino, JP;
Katsutaka Kimura, Akishima, JP;
Syunichi Saeki, Ome, JP;
Takashi Kobayashi, Tokorozawa, JP;
Yasushi Goto, Kokubunji, JP;
Tokuo Kure, Hinodemachi, JP;
Hideaki Kurata, Kokubunji, JP;
Hitoshi Kume, Musashino, JP;
Katsutaka Kimura, Akishima, JP;
Syunichi Saeki, Ome, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regionsformed first conduction type well, floating gatesformed on semiconductor substratethrough an insulator film, control gatesformed on floating gatesthrough nitrogen-introduced silicon oxide filmand third gatesdifferent from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gatesthus formed is made lower than that of floating gates, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.