The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 2006
Filed:
Mar. 04, 2005
Mihel Seitz, Radebeul, DE;
Stephan Wege, Weissig, DE;
Mihel Seitz, Radebeul, DE;
Stephan Wege, Weissig, DE;
Infineon Technologies AG, München, DE;
Abstract
The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate () made of silicon with a first hard mask layer () made of silicon oxide and an overlying second hard mask layer () made of silicon; providing a masking layer () made of silicon oxide above and laterally with respect to the second hard mask layer () made of silicon and above an uncovered edge region (RB) of the semiconductor substrate (); providing a photoresist mask () above the masking layer () with openings corresponding from trenches (DT) to be formed in the semiconductor substrate (); opening the masking layer () in a first plasma process using the photoresist mask (), the edge region (RB) being covered by a shielding device (AR); opening the first hard mask layer () and second hard mask layer () in a second and third plasma process; and forming the trenches (DT) in the semiconductor substrate () in a fourth plasma process using the opened first hard mask layer (); the edge region (RB) not being covered by the shielding device (AR) in the second to fourth plasma processes.