The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 2006
Filed:
Dec. 31, 2002
Kiyota Hachimine, Mitaka, JP;
Akihiro Shimizu, Fussa, JP;
Nagatoshi Ooki, Shimizu, JP;
Satoshi Sakai, Yokohama, JP;
Naoki Yamamoto, Kawaguchi, JP;
Kiyota Hachimine, Mitaka, JP;
Akihiro Shimizu, Fussa, JP;
Nagatoshi Ooki, Shimizu, JP;
Satoshi Sakai, Yokohama, JP;
Naoki Yamamoto, Kawaguchi, JP;
Renesas Technology Corp., Tokyo, JP;
Hitachi ULSI Systems Co., LTD, Tokyo, JP;
Abstract
A method of manufacturing a semiconductor device having an n-type FET and p-type FET, each formed over a semiconductor substrate, calls for (a) forming, over the n-type FET and p-type FET, a first insulating film, for generating a tensile stress in the channel formation region of the n-type FET, to cover gate electrodes of the FETs, while covering, with an insulating film, a semiconductor region between the gate electrode of the p-type FET and an element isolation region of the semiconductor substrate; (b) selectively removing the first insulating film from the upper surface of the p-type FET by etching; (c) forming, over the n-type and p-type FETs, a second insulating film, for generating a compressive stress in the channel formation region of the p-type FET, to cover gate electrodes of the FETs; and (d) selectively removing the second insulating film from the upper surface of the n-type FET.