The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2006

Filed:

Jun. 10, 2002
Applicants:

Michael A. Riepe, San Jose, CA (US);

Robert M. Swanson, Palo Alto, CA (US);

Timothy M. Burks, Palo Alto, CA (US);

Lukas Van Ginneken, San Jose, CA (US);

Karen F. Vahtra, Sunnyvale, CA (US);

Hamid Savoj, Los Altos, CA (US);

Inventors:

Michael A. Riepe, San Jose, CA (US);

Robert M. Swanson, Palo Alto, CA (US);

Timothy M. Burks, Palo Alto, CA (US);

Lukas van Ginneken, San Jose, CA (US);

Karen F. Vahtra, Sunnyvale, CA (US);

Hamid Savoj, Los Altos, CA (US);

Assignee:

Magma Design Automation, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for modeling integrated circuit designs in a hierarchical design automation system which utilizes a block abstraction including therein set of all database objects (cells, nets, wires, vias, and blockages) that are necessary to achieve accurate placement, routing, extraction, simulation, and verification of the block's ancestors in the hierarchy.


Find Patent Forward Citations

Riepe, Michael. (2006). Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system (U.S. Patent No. 7103863). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7103863

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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