The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2006

Filed:

Oct. 25, 2002
Applicants:

William R. Corbin, Underhill, VT (US);

Brian R. Kessler, Richmond, VT (US);

Erik A. Nelson, Waterbury, VT (US);

Thomas E. Obremski, So. Burlington, VT (US);

Donald L. Wheater, West Hinesburg, VT (US);

Inventors:

William R. Corbin, Underhill, VT (US);

Brian R. Kessler, Richmond, VT (US);

Erik A. Nelson, Waterbury, VT (US);

Thomas E. Obremski, So. Burlington, VT (US);

Donald L. Wheater, West Hinesburg, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

Technique to perform logic and embedded memory tests using logic scan chain testing procedures in parallel with memory built in self test (BIST). This is accomplished with a combination of voltage isolation between memory and logic segments, and isolation between logic and memory test clocks. A test algorithm is introduced to enable and disable the scan chain operation during BIST operation.


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