The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7102404 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 05, 2006

Filed:

Jun. 30, 2005
Applicant:

Chaiyuth Chansungsan, Aloha, OR (US);

Inventor:

Chaiyuth Chansungsan, Aloha, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); H03K 5/13 (2006.01);
U.S. Cl.
CPC ...
Abstract

An improved interpolator includes a replica delay line and an interpolated delay edge generator. The replica delay line provides two replica delay edges to the interpolated delay edge generator. The interpolated delay edge generator selectively generates an interpolated delay edge while maintaining a substantially constant capacitive loading on the two replica delay edges. The replica delay line may comprise a delay cell of four current-starved inverter delay stages or four capacitor-loaded inverter delay stages.


Find Patent Forward Citations

Chansungsan, Chaiyuth. (2006). Interpolator circuit (U.S. Patent No. 7102404). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7102404

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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