Semiconductor memory device having memory cells with floating gates and memory cell threshold voltage control method

Abstract

A semiconductor memory device includes a memory cell array, word lines, bit lines, a control circuit, and a measurement circuit. The memory cell array has memory cells including a floating gate. The control circuit performs first control to collectively shift the threshold voltages of the memory cells to within a predetermined range with a first level as an upper limit, second control to shift a lower limit of the threshold voltages toward a second level lower than the first level, and third control to shift the lower limit to a third level. The measurement circuit measures the elapsed time from the start of the second control. The control circuit repeats the second control, and then terminates the second control when the lower limit reaches the second level or the elapsed time measured by the measurement circuit reaches the predetermined time and performing the third control.