The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2006
Filed:
Sep. 24, 2004
Katherina E. Babich, Chappaqua, NY (US);
Roy Arthur Carruthers, Stormville, NY (US);
Timothy Joseph Dalton, Ridgefield, CT (US);
Alfred Grill, White Plains, NY (US);
Jeffrey Curtis Hedrick, Montvale, NJ (US);
Christopher Vincent Jahnes, Upper Saddle River, NJ (US);
Ebony Lynn Mays, Atlanta, GA (US);
Laurent Perraud, Paris, FR;
Sampath Purushothaman, Yorktown Heights, NY (US);
Katherine Lynn Saenger, Ossining, NY (US);
Katherina E. Babich, Chappaqua, NY (US);
Roy Arthur Carruthers, Stormville, NY (US);
Timothy Joseph Dalton, Ridgefield, CT (US);
Alfred Grill, White Plains, NY (US);
Jeffrey Curtis Hedrick, Montvale, NJ (US);
Christopher Vincent Jahnes, Upper Saddle River, NJ (US);
Ebony Lynn Mays, Atlanta, GA (US);
Laurent Perraud, Paris, FR;
Sampath Purushothaman, Yorktown Heights, NY (US);
Katherine Lynn Saenger, Ossining, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.