The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2006
Filed:
Jun. 12, 2003
Alan Barry Liu, Mountain View, CA (US);
Marc O. Schweitzer, San Jose, CA (US);
James Stephen Van Gogh, Sunnyvale, CA (US);
Michael Rosenstein, Sunnyvale, CA (US);
Jennifer L. Watia, Mountain View, CA (US);
Xinyu Zhang, Fremont, CA (US);
Yoichiro Tanaka, San Jose, CA (US);
John C. Forster, San Francisco, CA (US);
Anthony Chen, Los Altos Hills, CA (US);
Alan Barry Liu, Mountain View, CA (US);
Marc O. Schweitzer, San Jose, CA (US);
James Stephen Van Gogh, Sunnyvale, CA (US);
Michael Rosenstein, Sunnyvale, CA (US);
Jennifer L. Watia, Mountain View, CA (US);
Xinyu Zhang, Fremont, CA (US);
Yoichiro Tanaka, San Jose, CA (US);
John C. Forster, San Francisco, CA (US);
Anthony Chen, Los Altos Hills, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
In one embodiment, a target alignment surface disposed on a target support mechanically engages a darkspace shield alignment surface disposed on a darkspace shield as the target is lodged into a chamber body. The respective alignment surfaces are shaped and positioned so that the darkspace shield is physically moved to a desired aligned position as the alignment surfaces engage each other. In this manner a darkspace shield may be directly aligned to a target within a semiconductor fabrication chamber to provide a suitable darkspace gap between the target and the darkspace shield.