The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7094994 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 22, 2006

Filed:

Mar. 09, 2004
Applicants:

Kenichi Oyama, Kanagawa, JP;

Atsushi Someya, Kanagawa, JP;

Yuko Yamaguchi, Kanagawa, JP;

Inventors:

Kenichi Oyama, Kanagawa, JP;

Atsushi Someya, Kanagawa, JP;

Yuko Yamaguchi, Kanagawa, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05B 3/68 (2006.01); H05B 3/02 (2006.01); C23C 16/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor wafer heat treatment apparatus and method, which can carry out a heat treatment to suppress variations in line widths within a surface on a semiconductor wafer and the like, includes: a heating plate for heating a semiconductor wafer to a predetermined temperature; a temperature measuring unit for measuring temperatures when heating the semiconductor wafer or a semiconductor wafer equivalent placed on the heating plate, at portions divided into a plurality of regions; and a controller for controlling the temperatures of the semiconductor wafer, and based on the temperature measurement result of the temperature measuring unit, the controller controls the temperature in heating the semiconductor wafer, for each of the plurality of regions. In cooling after the heating process, based on the temperature measurement result, the controller controls the temperature in cooling the semiconductor wafer, for each of the plurality of regions.


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Oyama, Kenichi. (2006). Heat treatment apparatus and method of semiconductor wafer (U.S. Patent No. 7094994). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7094994

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