The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2006
Filed:
Jan. 20, 2005
Nirmal Chaudhary, Austin, TX (US);
Thomas Schulz, Austin, TX (US);
Weize Xiong, Austin, TX (US);
Craig Huffman, Austin, TX (US);
Nirmal Chaudhary, Austin, TX (US);
Thomas Schulz, Austin, TX (US);
Weize Xiong, Austin, TX (US);
Craig Huffman, Austin, TX (US);
Infineon Technologies AG, Munich, DE;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs. The self-planarizing conductive layer is characterized by a substantially flatter surface than the underlying topography. As a result of the self-planarizing layer, a masking layer having a more uniform thickness may be formed over the conductive layer. Because the masking layer has a more uniform thickness, the masking layer may easily be patterned without causing damage to the underlying materials. These techniques may be used to fabricate, among other things, a FinFET without parasitic spacers formed around the fins and the source/drain regions.