The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7093224 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 15, 2006

Filed:

Aug. 28, 2001
Applicants:

William R. Wheeler, Southborough, MA (US);

Matthew J. Adiletta, Worcester, MA (US);

Christopher Clark, Hopkinton, MA (US);

Timothy J. Fennel, Holliston, MA (US);

Inventors:

William R. Wheeler, Southborough, MA (US);

Matthew J. Adiletta, Worcester, MA (US);

Christopher Clark, Hopkinton, MA (US);

Timothy J. Fennel, Holliston, MA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A technique for designing a logic circuit includes specifying a model. The model including combinatorial blocks, state elements and graphical library elements. The technique maintains a data structure representative of the model, and generates an architectural model and an implementation model from the data structure. The data structure represents a descriptive net list of the model. The architectural model includes C++ code and the implementation model includes Verilog.


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